1. Field of Invention
The present application relates to the general area of integrated circuit (IC) manufacture and more particularly to methods and systems for creating and using a data store of profile-based simulations information.
2. Related Art
With the demand for increasing clock rates and decreasing geometries of IC structures, there is a need for rapid feedback on the effect of wafer design and fabrication process decisions. In many traditional IC manufacturing environments, the effect of a design decision or a fabrication process change is frequently not immediately known by the designers or the process engineers until much later, resulting in costly rework or unusable end products. IC design objectives drive the design activity where masks and IC fabrication plans are produced and transmitted to IC fabrication. IC fabrication produces the wafers that are tested and that undergo finishing operations in IC testing and finishing where flaws or shortcomings of the wafer are noted. Typically, some of the impact of design or process decisions is fed back to the design and fabrication groups at this point. After shipment of the products to the customers, additional product feedback that relate to design and process alterations eventually get back to IC design. It is well known in the industry that detection of a bad chip at the wafer level is much cheaper than detecting the bad chip after many end-products have been shipped to the customers. Thus, there is a need to provide information about the impact of design and process changes as early as possible.
In a similar manner, there is a dearth of immediate feedback on design and process decisions to the manufacturing process control group. FIG. 1 is a prior art architectural diagram illustrating the flow of data from IC manufacturing process control to the various fabrication areas and feedback from the fabrication areas to IC manufacturing process control. The IC manufacturing objectives 21 directs the IC manufacturing process control 23 group with manufacturing plans 24 related to thin film processes, deposition, or chemical mechanical polishing (CMP) 25, lithography 27, etching 29, photoresist (PR) stripping 33 and 35, implantation 31, and thermal processes 37 and IC testing and packaging 39. Process feedback 34 and design and overall fabrication feedback 32 are sent to the IC manufacturing process control 23 group. However, if a design did not produce the desired results or a process change caused some key critical dimension (CD) of the structures to be out of the acceptable ranges, the batch of wafers affected may have to be discarded. Thus, there is a need to provide information in-line to the IC manufacturing process control group in order to minimize rejected wafers and to detect and correct process control parameters from drift or process control parameter variations. Even with the use of current design and fabrication process simulators, there is typically insufficient information available early and/or in-line with the fabrication process.
There are several fabrication process, device, and circuit simulators currently in use. Examples include software capable of interconnect simulation, lithography simulation, implantation simulation, diffusion simulation, oxidation simulation, deposition and etching simulation, CMP simulation, deposition and reflow simulation, 2-dimensional process simulation, and 3-dimensional fabrication process simulation, and others capable of simulating a step or series of steps of the IC fabrication process. Some simulators assume simple geometric shapes of IC structures. However, data provided by AFM, Cross-Section SEM (X-SEM), and optical metrology systems indicate the cross-sections of structures are complex shapes. These complex-shaped structures provide different electrical, thermal, and performance properties than the typical geometric shapes assumed. Other simulators attempt to model complex shapes with limited success due to the number of variables during fabrication. For example, the structure shape is greatly influenced by the process control parameters such as lithography numerical aperture, wavelength, focus exposure, post exposure bake (PEB) temperature, resist thickness, anti-reflective coating thickness, dielectric materials, and fabrication processes used.
As technology heads into the deep submicron geometries, (0.250 micron or less), there is a greater need for fast and accurate information relating to fabrication process attributes such as structure profiles, device attributes such as capacitance, inductance, and resistance and ultimately circuit attributes. Similarly, there is a need for fast and reliable information for process control parameters such as PEB temperature, focus, and exposure that generate the desired IC structure profiles that in turn provide the desired device and circuit attributes. Thus, there is a need for a method and/or system for making the information on profile data, signals, process control parameters, and process attributes available during the fabrication process. Alternatively, given a structure profile or process attribute target, there is a need for rapid information on the process control parameter values that would provide the desired results. For example, it is advantageous to know the combination of PEB temperature, time, numerical aperture, and focus required to fabricate a structure with the desired profile that delivers the required electrical, thermal, and performance properties.